In 2003, the PCI SIG ratified PCI-X 2.0. It adds 266-MHz and 533-MHz variants, acquiescent almost 2.15 GB/s and 4.3 GB/s throughput, respectively. PCI-X 2.0 makes added agreement revisions that are advised to advice arrangement believability and add Error-correcting codes to the bus to abstain re-sends.1 To accord with one of the a lot of accepted complaints of the PCI-X anatomy factor, the 184-pin connector, 16-bit ports were developed to acquiesce PCI-X to be acclimated in accessories with bound amplitude constraints. Similar to PCI-Express, PtP functions were added to acquiesce for accessories on the bus to allocution to anniversary added after burdening the CPU or bus controller.
Despite the assorted abstract advantages of PCI-X 2.0 and its astern affinity with PCI-X and PCI devices, it has not been implemented on a ample calibration (as of 2008). This abridgement of accomplishing primarily is because accouterments vendors accept called to accommodate PCI Express instead.
Despite the assorted abstract advantages of PCI-X 2.0 and its astern affinity with PCI-X and PCI devices, it has not been implemented on a ample calibration (as of 2008). This abridgement of accomplishing primarily is because accouterments vendors accept called to accommodate PCI Express instead.
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