PCI-X, abbreviate for PCI-eXtended, is a computer bus and amplification agenda accepted that enhances the 32-bit PCI Local Bus for college bandwidth accepted by servers. It is a double-wide adaptation of PCI, active at up to four times the alarm speed, but is contrarily agnate in electrical accomplishing and uses the aforementioned protocol.1 It has been replaced in avant-garde designscitation needed by the similar-sounding PCI Express, with a absolutely altered adapter and a actual altered analytic design, getting a individual attenuated but fast consecutive affiliation instead of a amount of slower access in parallel. There is aswell a 64-bit PCI blueprint electrically altered but with the aforementioned adapter as PCI-X.
Monday, February 6, 2012
Background
PCI-X was developed accordingly by IBM, HP, and Compaq and submitted for approval in 1998. It was an accomplishment to arrange proprietary server extensions to the PCI bounded bus to abode several shortcomings in PCI, and access achievement of top bandwidth devices, such as Gigabit Ethernet, Fibre Channel, and Ultra3 SCSI cards, and acquiesce processors to be commutual in clusters.
In PCI, a transaction that cannot be completed anon is adjourned by either the ambition or the architect arising retry-cycles, during which no added agents can use the PCI bus. Since PCI lacks a split-response apparatus to admittance the ambition to acknowledgment abstracts at a afterwards time, the bus charcoal active by the ambition arising retry-cycles until the apprehend abstracts is ready. In PCI-X, afterwards the adept issues the request, it disconnects from the PCI bus, acceptance added agents to use the bus. The split-response absolute the requested abstracts is generated alone if the ambition is accessible to acknowledgment all of the requested data. Split-responses access bus ability by eliminating retry-cycles, during which no abstracts can be transferred above the bus.
PCI aswell suffered from the about absence of different arrest lines. With alone 4 arrest curve (INTA/B/C/D), systems with abounding PCI accessories crave assorted functions to allotment an arrest line, complicating host-side interrupt-handling. PCI-X added MSI, an arrest arrangement application writes to host-memory. In MSI-mode, the function's arrest is not signaled by asserting an INTx line. Instead, the action performs a memory-write to a system-configured arena in host-memory. Since the agreeable and abode are configured on a per-function basis, MSI-mode interrupts are committed instead of shared. A PCI-X arrangement allows both MSI-mode interrupts and bequest INTx interrupts to be acclimated accompanying (though not by the aforementioned function.)
The abridgement of registered I/Os bound PCI to a best abundance of 66 MHz. PCI-X I/Os are registered to the PCI clock, usually through agency of a PLL to actively ascendancy I/O adjournment the bus pins. The advance in bureaucracy time allows an access in abundance to 133 MHz.
Some devices, a lot of conspicuously Gigabit Ethernet cards, SCSI controllers (Fibre Channel and Ultra320), and array interconnects could by themselves bathe the PCI bus' 133 MB/s bandwidth. Ports application a bus acceleration angled to 66 MHz and a bus amplitude angled to 64 $.25 (with the pin calculation added to 184 from 124), in aggregate or not, accept been implemented. These extensions were about accurate as alternative locations of the PCI 2.x standards, but accessory affinity above the basal 133 MB/s connected to be difficult.
Developers eventually acclimated the accumulated 64-bit and 66-MHz addendum as a foundation, and, anticipating approaching needs, accustomed 66-MHz and 133-MHz variants with a best bandwidth of 532 MB/s and 1064 MB/s respectively. The collective aftereffect was submitted as PCI-X to the PCI Special Interest Group (Special Interest Group of the Association for Computing Machinery). Subsequent approval fabricated it an accessible accepted adoptable by all computer developers. The PCI SIG controls abstruse support, training, and acquiescence testing for PCI-X. IBM, Intel, Microelectronics, and Mylex were to advance acknowledging chipsets. 3Com and Adaptec were to advance accordant peripherals. To advance PCI-X acceptance by the industry, Compaq offered PCI-X development accoutrement at their Web site. All above dent makers about now accept or accept had some alternative of PCI-X in their artefact lines.
In PCI, a transaction that cannot be completed anon is adjourned by either the ambition or the architect arising retry-cycles, during which no added agents can use the PCI bus. Since PCI lacks a split-response apparatus to admittance the ambition to acknowledgment abstracts at a afterwards time, the bus charcoal active by the ambition arising retry-cycles until the apprehend abstracts is ready. In PCI-X, afterwards the adept issues the request, it disconnects from the PCI bus, acceptance added agents to use the bus. The split-response absolute the requested abstracts is generated alone if the ambition is accessible to acknowledgment all of the requested data. Split-responses access bus ability by eliminating retry-cycles, during which no abstracts can be transferred above the bus.
PCI aswell suffered from the about absence of different arrest lines. With alone 4 arrest curve (INTA/B/C/D), systems with abounding PCI accessories crave assorted functions to allotment an arrest line, complicating host-side interrupt-handling. PCI-X added MSI, an arrest arrangement application writes to host-memory. In MSI-mode, the function's arrest is not signaled by asserting an INTx line. Instead, the action performs a memory-write to a system-configured arena in host-memory. Since the agreeable and abode are configured on a per-function basis, MSI-mode interrupts are committed instead of shared. A PCI-X arrangement allows both MSI-mode interrupts and bequest INTx interrupts to be acclimated accompanying (though not by the aforementioned function.)
The abridgement of registered I/Os bound PCI to a best abundance of 66 MHz. PCI-X I/Os are registered to the PCI clock, usually through agency of a PLL to actively ascendancy I/O adjournment the bus pins. The advance in bureaucracy time allows an access in abundance to 133 MHz.
Some devices, a lot of conspicuously Gigabit Ethernet cards, SCSI controllers (Fibre Channel and Ultra320), and array interconnects could by themselves bathe the PCI bus' 133 MB/s bandwidth. Ports application a bus acceleration angled to 66 MHz and a bus amplitude angled to 64 $.25 (with the pin calculation added to 184 from 124), in aggregate or not, accept been implemented. These extensions were about accurate as alternative locations of the PCI 2.x standards, but accessory affinity above the basal 133 MB/s connected to be difficult.
Developers eventually acclimated the accumulated 64-bit and 66-MHz addendum as a foundation, and, anticipating approaching needs, accustomed 66-MHz and 133-MHz variants with a best bandwidth of 532 MB/s and 1064 MB/s respectively. The collective aftereffect was submitted as PCI-X to the PCI Special Interest Group (Special Interest Group of the Association for Computing Machinery). Subsequent approval fabricated it an accessible accepted adoptable by all computer developers. The PCI SIG controls abstruse support, training, and acquiescence testing for PCI-X. IBM, Intel, Microelectronics, and Mylex were to advance acknowledging chipsets. 3Com and Adaptec were to advance accordant peripherals. To advance PCI-X acceptance by the industry, Compaq offered PCI-X development accoutrement at their Web site. All above dent makers about now accept or accept had some alternative of PCI-X in their artefact lines.
Technical description
PCI-X revised the accepted PCI accepted by acceleration the best alarm acceleration (from 66 MHz to 133 MHz)1 and appropriately the bulk of abstracts exchanged amid the computer processor and peripherals. Accepted PCI supports up to 64 $.25 at 66 MHz (though annihilation aloft 32 $.25 at 33 MHz is apparent alone in high-end systems) and added bus standards move 32 $.25 at 66 MHz or 64 $.25 at 33 MHz. The abstract best bulk of abstracts exchanged amid the processor and peripherals with PCI-X is 1.06 GB/s, compared to 133 MB/s with accepted PCI. PCI-X aswell improves the accountability altruism of PCI, allowing, for example, adulterated cards to be reinitialized or taken offline.
PCI-X is not accordant with the earlier 5-volt I/O, which the aboriginal afterlight of PCI acclimated exclusively. Starting with PCI 2.x, 3.3 volt I/O was supported, with which PCI-X is astern compatible.1 Apart from this, PCI-X and 3.3 volt PCI cards about can be intermixed on a PCI-X bus, but bus acceleration will be bound to the alarm abundance of the slowest card, an inherent limitation of PCI's aggregate bus topology. For example, if a PCI 2.3, 66-MHz borderline is installed into a PCI-X bus able of 133 MHz, the absolute bus backplane will be bound to 66 MHz. To get about this limitation and the voltage affinity issue, abounding motherboards accept assorted PCI/PCI-X buses, with one bus advised for use with accelerated PCI-X peripherals, and the added bus advised for general-purpose peripherals.
edit Distinction from 64-bit PCI
The 64-bit PCI adapter can be acclaimed from 32-bit by getting longer, and from PCI-X by accepting three segments, with the one in the average abundant beneath than the others. PCI-X slots can be acclaimed from 64-bit PCI as the baby articulation is first, instead of in the center. 32-bit PCI cards will action appropriately in a PCI-X slot, but PCI-X cards do not plan in a accepted 32 bit PCI slot.2. Abounding 64-bit PCI cards are advised to action normally, with some accident of speed, in 32-bit slots3.
PCI-X is not accordant with the earlier 5-volt I/O, which the aboriginal afterlight of PCI acclimated exclusively. Starting with PCI 2.x, 3.3 volt I/O was supported, with which PCI-X is astern compatible.1 Apart from this, PCI-X and 3.3 volt PCI cards about can be intermixed on a PCI-X bus, but bus acceleration will be bound to the alarm abundance of the slowest card, an inherent limitation of PCI's aggregate bus topology. For example, if a PCI 2.3, 66-MHz borderline is installed into a PCI-X bus able of 133 MHz, the absolute bus backplane will be bound to 66 MHz. To get about this limitation and the voltage affinity issue, abounding motherboards accept assorted PCI/PCI-X buses, with one bus advised for use with accelerated PCI-X peripherals, and the added bus advised for general-purpose peripherals.
edit Distinction from 64-bit PCI
The 64-bit PCI adapter can be acclaimed from 32-bit by getting longer, and from PCI-X by accepting three segments, with the one in the average abundant beneath than the others. PCI-X slots can be acclaimed from 64-bit PCI as the baby articulation is first, instead of in the center. 32-bit PCI cards will action appropriately in a PCI-X slot, but PCI-X cards do not plan in a accepted 32 bit PCI slot.2. Abounding 64-bit PCI cards are advised to action normally, with some accident of speed, in 32-bit slots3.
Versions
All PCI-X cards or slots accept a 64-bit accomplishing and alter as follows:
Cards
66 MHz (added in Rev. 1.0)1
100 MHz (implemented by a 133 MHz adapter on some servers)4
133 MHz (added in Rev. 1.0)1
266 MHz (added in Rev. 2.0)1
533 MHz (added in Rev. 2.0)1
Slots
66 MHz (can be begin on earlier servers)
133 MHz (most accepted on avant-garde servers)
266 MHz (rare, getting replaced by PCI-e)
533 MHz (rare, getting replaced by PCI-e)
Cards
66 MHz (added in Rev. 1.0)1
100 MHz (implemented by a 133 MHz adapter on some servers)4
133 MHz (added in Rev. 1.0)1
266 MHz (added in Rev. 2.0)1
533 MHz (added in Rev. 2.0)1
Slots
66 MHz (can be begin on earlier servers)
133 MHz (most accepted on avant-garde servers)
266 MHz (rare, getting replaced by PCI-e)
533 MHz (rare, getting replaced by PCI-e)
PCI-X 2.0
In 2003, the PCI SIG ratified PCI-X 2.0. It adds 266-MHz and 533-MHz variants, acquiescent almost 2.15 GB/s and 4.3 GB/s throughput, respectively. PCI-X 2.0 makes added agreement revisions that are advised to advice arrangement believability and add Error-correcting codes to the bus to abstain re-sends.1 To accord with one of the a lot of accepted complaints of the PCI-X anatomy factor, the 184-pin connector, 16-bit ports were developed to acquiesce PCI-X to be acclimated in accessories with bound amplitude constraints. Similar to PCI-Express, PtP functions were added to acquiesce for accessories on the bus to allocution to anniversary added after burdening the CPU or bus controller.
Despite the assorted abstract advantages of PCI-X 2.0 and its astern affinity with PCI-X and PCI devices, it has not been implemented on a ample calibration (as of 2008). This abridgement of accomplishing primarily is because accouterments vendors accept called to accommodate PCI Express instead.
Despite the assorted abstract advantages of PCI-X 2.0 and its astern affinity with PCI-X and PCI devices, it has not been implemented on a ample calibration (as of 2008). This abridgement of accomplishing primarily is because accouterments vendors accept called to accommodate PCI Express instead.
Confusion with PCI-Express
PCI-X is generally abashed by name with PCI Express, frequently abbreviated as PCI-E or PCIe, although the cards themselves are absolutely adverse and attending different. The acumen for this abashing is that "PCI-X" sounds agnate to "PCI Express". While they are both accelerated computer buses for centralized peripherals, they alter in abounding ways. The aboriginal is that PCI-X is a alongside interface that is anon astern accordant with all but the oldest (5-volt) accepted PCI devices. PCIe is a consecutive bus with a altered concrete interface that was advised to abandon both PCI and PCI-X.
PCI-X and accepted PCI buses may run on a PCIe bridge, agnate to the way ISA buses ran on accepted PCI buses in some computers. PCIe aswell matches PCI-X and even PCI-X 2.0 in best bandwidth. PCIe 1.0 x1 offers 250 MB/s in anniversary direction, and up to 32 lanes (x32) is currently supported, giving a best of 8 GB/s in anniversary direction.
PCI-X has abstruse and economical disadvantages compared to PCI-Express. The 64-bit alongside interface requires difficult trace routing, because, as with all alongside interfaces, the signals from the bus have to access accompanying or aural a actual abbreviate window, and babble from adjoining slots may could cause interference. The consecutive interface of PCIe suffers beneath such problems and accordingly does not crave such circuitous and big-ticket designs. PCI-X buses, like accepted PCI, are half-duplex bidirectional, admitting PCIe buses are full-duplex bidirectional. PCI-X buses run alone as fast as the slowest device, admitting PCIe accessories are able to apart accommodate the bus speed. Also, PCI-X slots are best than PCIe 1x through PCIe 16x, which makes it absurd to accomplish abbreviate cards for PCI-X. PCI-X slots yield absolutely a bit of amplitude on motherboards, which can be a botheration for ATX and abate anatomy factors.
PCI-X and accepted PCI buses may run on a PCIe bridge, agnate to the way ISA buses ran on accepted PCI buses in some computers. PCIe aswell matches PCI-X and even PCI-X 2.0 in best bandwidth. PCIe 1.0 x1 offers 250 MB/s in anniversary direction, and up to 32 lanes (x32) is currently supported, giving a best of 8 GB/s in anniversary direction.
PCI-X has abstruse and economical disadvantages compared to PCI-Express. The 64-bit alongside interface requires difficult trace routing, because, as with all alongside interfaces, the signals from the bus have to access accompanying or aural a actual abbreviate window, and babble from adjoining slots may could cause interference. The consecutive interface of PCIe suffers beneath such problems and accordingly does not crave such circuitous and big-ticket designs. PCI-X buses, like accepted PCI, are half-duplex bidirectional, admitting PCIe buses are full-duplex bidirectional. PCI-X buses run alone as fast as the slowest device, admitting PCIe accessories are able to apart accommodate the bus speed. Also, PCI-X slots are best than PCIe 1x through PCIe 16x, which makes it absurd to accomplish abbreviate cards for PCI-X. PCI-X slots yield absolutely a bit of amplitude on motherboards, which can be a botheration for ATX and abate anatomy factors.
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